1. Field of Use
The present invention relates to electronic integrated circuits (ICs) and, more particularly, to circuits which employ a standard boundary scan test access port.
2. Prior Art
A standard boundary scan test architecture was approved by the American National Standards Institute and the Institute of Electrical and Electronics Engineers in 1990. This architecture provides a means by which ICs may be designed in a standard fashion such that they or their external connections, or both, may be tested using a four or five wire interface.
The device test logic which connects to this interface is known as a test access port, or TAP. Device outputs normally controlled by the functional system logic of an IC chip may be controlled via the TAP. Also, device inputs to the functional system logic may be monitored via the TAP. All TAP control and data bits are passed in serial fashion on two lines: a test data input (TDI), and the test data output (TDO). Integral to each TAP is a TAP controller having a state machine which determines the function of the device test logic. A test clock (TCK) line and a test mode select (TMS) line determine the currently active state of each state machine. The state machine has been designed such that a logic one present at the TMS input for five consecutive clocks of TCK always results in placing the state machine in a state called test logic reset. In this state, the device test logic has no effect on the IC device functional logic circuits and the device operates essentially as if the test logic were not present. An optional test reset state (TRST*) line may be included in devices where there is a need to enter the test logic reset state without waiting for five TCK clock cycles. For example, such need may arise when there are possible output driver conflicts with other devices immediately after power up.
For compliance, the standard mandates the use of several specific operating modes for all devices while others are optional. For example, one mandated mode is known as EXTEST. This mode allows interconnections between devices to be checked by setting various outputs to known states and checking the receipt of these known states at various inputs to verify continuity. Additionally, through the use of potentially conflicting output states, the receipt of proper input states can verify the absence of shorts.
Optional modes include modes which, if present, must conform to the standard, and modes which are not defined by the standard. An example of the former is known as INTEST. This mode allows device functional logic inputs to be controlled via the TAP and device functional outputs to be monitored via the TAP. The INTEST mode allows the device functional logic circuits to be checked by applying test vectors and monitoring device response via the TAP. Modes not defined by the standard are known as private modes. An example of such a mode is a mode in which the TAP controls data shifting through an internal scan chain.
A register known as the instruction register is used to select the various operating modes of the TAP controlled test logic. Input bits destined for the TAP instruction register enter the device via the same interface line used for test data bits. The value of the data or instruction bits is determined by the current state of the TAP state machine. The length of the scan chain through the device (i.e., from the TDI line to the TDO line) is, therefore, determined by the length of the currently selected register.
The standard mandates the use of a number of registers. These registers, connected in parallel between a common serial input (TDI) and common serial output (TDO), include a bypass register, a boundary scan register and a number of optional test data registers. The length of the bypass register is defined as one bit. The instruction register has a minimum length of two bits and may be expanded as a user sees fit. For example, a 16-bit or longer instruction register may be appropriate for some applications.
During normal operation, all devices of a boundary scan chain are in the same TAP state machine state at any given time. Hence, it can be seen that the overall length of the boundary scan chain can vary widely depending upon the TAP selection of instruction versus data registers. While the length of the boundary scan chain may be minimized during the shifting of data bits by selecting the bypass register in some devices, it cannot be prevented from being expanded to the cumulative length of all device instruction registers during the shifting of instruction bits. Furthermore, since all instruction registers of the boundary scan chain must be updated together, an appropriate value must be determined for and shifted into all such instruction registers, not just the one or more instruction registers of immediate interest.
The inability to select particular devices of a boundary scan chain to receive instruction register updates, therefore, results in considerable overhead. To alter the contents of only one instruction register, the present state of all other instruction registers of the chain have to be determined and the appropriate bits made to proceed and follow the bits scanned into the instruction register of interest. For example, consider a boundary scan chain of a thousand serially connected devices, each having an instruction register 16 bits in length. To alter the 16-bit instruction register of one device, 16,000 bits would have to be shifted into the boundary scan chain once instruction register shifting was established. The shifting of 15,984 bits is viewed as overhead, since such shifting merely serves to restore the current contents of the other instruction registers not being altered. The overhead exists both in terms of time needed to shift in the bits and in the means needed in their determination.
It will be appreciated that the case where overhead would be somewhat minimized by specific instruction bit configurations and relative locations on the boundary scan chain has not been considered in the above example because of the greater importance of considering a general case.
Considerable overhead can also exist in the shifting of data bits. For example, again consider the case of a thousand devices in a single boundary scan chain. Assume, by virtue of previous instruction register entries, 999 devices have selected the bypass register and one device has selected an optional data register of 100 bits, for a total scan chain length of 1099 bits. Further, assume that it is desired to examine the contents of the optional data register each time new contents are shifted into the devices. In this case, up to 1099 shifts would be required for each change of the optional 100-bit data register, resulting in an overhead of 999 bits. Since the standard mandates loading the bypass register with a logic zero at the same time the optional data register is loaded, as determined by the state machine, the shifted data cannot be retained in the bypass registers to alleviate the overhead condition.
Overhead in boundary scan operations is significant in that it decreases the number of tests that may be conducted within a reasonable amount of time and increases the amount of external hardware and associated software needed to apply those tests.
Despite the powerful capability of the architecture defined by the standard, implementation at the level of a large board or at the system level can present problems in terms of selecting boundary scan paths of manageable length during design.
Other problems also exist in determining boundary scan paths. One such problem is the case where electrical faults or shortcomings of the test interface, as with the clock line (TCK) cause erratic test operation. In this case, diagnosing and locating the fault within the test interface and its associated logic becomes more difficult as the length of the boundary scan chain increases.
Experts in the field have attempted to increase boundary scan chain manageability by creating multiple chains which are merged into a single interface grouping by means of added controller devices which have attributes similar to TAPs. One such device is the "Backplane Test Bus Link" described by D. Bhavsar in the published proceedings of the 1991 IEEE International Test Conference." Another such device is the "Addressable Shadow Port" described by L. Whetsel in the published proceedings of the 1992 IEEE International Test Conference.
These and similar such devices represent an overhead of a different kind. They have hardware overhead beyond that which is already contained in devices having TAP controllers that conform to the above mentioned standard. In certain cases, such devices and methods could be implemented as additions to devices already defined to be incorporated as part of a given design. However, whether or not such methods are implemented as dedicated devices or incorporated as part of an integrated circuit during design, they still represent an undesirable hardware overhead in the general case.
Accordingly, it is a primary object of the present invention to provide a method and means of minimizing the bit overhead of the boundary scan serial string test operations without incurring the overhead typically found in attempts to implement boundary scan in a multiplicity of strings at a board or system level.
It is a further object of the present invention to provide such method and means of minimizing bit overhead in a manner which does not conflict with present standards to the extent that devices incorporating the present invention could be used with devices previously manufactured to conform to the standard.
It is a still further object of the present invention to provide a method and apparatus for performing verification and diagnostic operations relating to the device test logic.